1. Field of the Invention
The present invention relates to an output buffer circuit, and more specifically to an output buffer circuit composed of MOS transistors (metal-oxide-semiconductor field effect transistors) and for use in an integrated circuit.
2. Description of Related Art
Recently, integrated circuits is increasing its field of application, and at present have been actually utilized for the control purpose in various fields including an office instrument, an in-house electric instrument, an automobile, etc. As one of various functions of the control-purpose integrated circuits used in the various fields, it is required to internally contain a so called slew rate output buffer.
The slew rate output buffer in a MOSIC (MOS transistor integrated circuit) is a buffer in which an output waveform changes at a low speed when an buffer output changes front a high level to a low level or vice versa, in order to avoid all of MOS transistors driving an output terminal, from being put into an ON condition simultaneously. This output buffer function is effective in preventing generation of noises on a voltage supply line or a ground line in the MOSIC, and also in preventing an overshooting or an undershooting from occurring in the output voltage waveform of the output buffer.
Referring to FIG. 1, there is shown a circuit diagram illustrating one example of a conventional slew rate output buffer circuit in a CMOS (complementary MOS transistor) technology. The shown buffer circuit basically includes an output driving stage composed of a P-channel transistor 310 and an N-channel transistor 311 having their drain electrode connected in common to an output terminal 312. The P-channel transistor 310 has a source electrode connected to a voltage supply line VDD and a gate electrode connected to one end of a capacitor 308, the other end of which is connected to the voltage supply line VDD. The N-channel transistor 311 has a source electrode connected to a ground line and a gate electrode connected to one end of a capacitor 309, the other end of which is connected to the ground line. Here, each of the capacitors 308 and 309 includes a capacitance of the gate electrode of the MOS transistor connected with the capacitor concerned.
An input terminal 301 is connected to an input of each of inverters 302 and 303, which cooperate with the input terminal to control a charging/discharging timing of the capacitors 308 and 309. For this purpose, an output of the inverter 302 is connected through a resistor 304 to the one end of the capacitor 308 so as to charge the capacitor 308 to a ground level. A P-channel transistor 306 having its gate connected to the input terminal 301, its source connected to the voltage supply line VDD and its drain connected to the one end of the capacitor 308, acts to discharge the capacitor 308 to a voltage supply level. An output of the inverter 303 is connected through a resistor 305 to the one end of the capacitor 309 so as to charge the capacitor 309 to the voltage supply level. An N-channel transistor 307 having its gate connected to the input terminal 301, its source connected to the ground line and its drain connected to the one end of the capacitor 309, acts to discharge the capacitor 309 to ground level.
Now, operation of the circuit shown in FIG. 1 will be described with reference to FIG. 2, which illustrates waveforms on various points in the circuit shown in FIG. 1.
When an input voltage applied to the input terminal 301 is a low level, the P-channel transistor 306 is on, so that the capacitor 308 is in a condition discharged to the voltage supply level. On the other hand, the N-channel transistor 307 is off, so that the capacitor 309 is in a condition charged to the voltage supply level through the resistor 305 from the output of the inverter 303. Therefore, the output driving P-channel transistor 310 is off and the output driving N-channel transistor 311 is on, so that an voltage on the output terminal 312 is at a ground level.
When the input voltage of the input terminal 301 rises up from the low level to a high level, the output of the inverter 303 changes to the ground level, and simultaneously, the N-channel transistor 307 is brought from the off condition to the on condition, so that the capacitor 309 is discharged to the ground level, and therefore, the output driving N-channel transistor 311 is immediately turned off.
On the other hand, the P-channel transistor 306 is brought from the on condition to the off condition, and simultaneously, the output of the inverter 302 changes to the ground level. Here, since the capacitor 308 is charged by the output of the inverter 302 through the resistor 304 towards the ground level, the potential on the one end of the capacitor 308 gradually shifts to the ground level. Therefore, the output voltage on the output terminal 312 slowly rises up with a substantial rising time.
Similarly, when the input voltage of the input terminal 301 falls down from the high level to the low level, the capacitor 308 is discharged to the voltage supply level, so that the output driving P-channel transistor 310 is immediately turned off. But, the capacitor 309 is charged through the resistor 305, the potential of the capacitor 309 gradually shifts towards the voltage supply level. Accordingly, the output voltage on the output terminal 312 slowly falls down with a substantial rising time.
Referring to FIG. 3, there is shown a circuit diagram of another conventional output buffer circuit shown in FIG. 2 of Japanese Patent Application Laid-open Publication No. JP-A-2-122725.
The output buffer circuit shown in FIG. 3 is configured to be capable of selecting the rising time and the failing time between a high speed value and a low speed value by means of a control terminal 502 in accordance with an application thereof.
When a signal applied to the control terminal 502 is at a low level, both of an N-channel transistor 507 and a P-channel transistor 508 are off, so that when an output driving MOS transistor is turned on, inverters 503 and 505 having a small driving power will drive a gate of an output driving P-channel transistor 510 and an output driving N-channel transistor 511 with the small drive power, so as to turn on the output driving transistor with a slow driving speed. Therefore, an output voltage of an output terminal 512 has a slow rising time and a slow falling time.
When the signal applied to the control terminal 502 is at a high level, both of the N-channel transistor 507 and the P-channel transistor 508 are on. An N-channel transistor 506 and a P-channel transistor 509 cooperate with the inverters 503 and 505, respectively, to drive the gate of the output driving P-channel transistor 510 and the output driving N-channel transistor 511 with a large drive power, so as to turn on the output driving transistor with a high driving speed. Therefore, the output voltage of the output terminal 512 has a high rising time and a high falling time.
The above mentioned conventional output buffer circuits are so designed that, in order to make slow the rising and the falling of the output voltage on the output terminal, the capacitor means including a gate capacitance of the output driving MOS transistor is gradually charged through a resistor means, so as to turn on the output driving MOS transistor at a low speed.
Because of this reason, the time after the input voltage of the input terminal changes until the potential of the capacitor means is charged to a threshold voltage of the output driving MOS transistor, becomes long, as shown in FIG. 2, and therefore, the rising/falling propagation delay time of the output voltage becomes correspondingly long, as also shown in FIG. 2. In addition, a variation in phase of output signals become large dependently upon a manufacturing condition and a operation condition, so that it is not possible to elevate an operating frequency of the overall system.